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datasheet d s _ d c t 12s0a0s0 3 n fa _ 11142013 features ? high efficiency : 9 4. 9 % @ 12 vin , 5 v/ 3 a out ? small size and low profile: ? 12.2x 12.2x 7. 4 5mm (0.48 x 0.48 x 0.29 3 ) ? surface mount packaging ? standard footprint ? voltage and r esistor - based trim ? pr e - bias startup ? output voltage tracking ? no minimum load required ? output voltage programmable from 0. 59 vdc to 5. 0 vdc via external resistor ? fixed frequency operation ? input uvlo , output ocp ? remote on/off ? iso 900 1 , tl 9000, iso 14001, qs9000, ohsas1800 1 certified manufacturing facility ? ul/cul 60950 - 1 (us & canada) ? ce mark meets 73/23/eec and 93/68/eec directives applications ? telecom / datacom ? distributed power architectures ? servers and work stations ? lan / wan applications ? data processing application s options ? negative /positive on/off logic ? tracking feature delphi d c t , non - isolated point of load dc/dc power modules: 4.5~14 v in , 0.59 - 5 .0 v / 3 a out the delphi series dc t , 4.5 - 1 4 v input, single output , non - isolated point of load dc/dc converters are the latest offering from a world leader in p ower systems technology and manufacturing -- d elta electronics, inc. the d c t series provides a programmable output voltage from 0. 59 v to 5.0 v using an external resistor and has flexible and programmable tracking fe atures to enable a variety of startup voltages as well as tracking between power modules . this product family is available in surface mount and provides up to 3 a of output current in an industry standard footprint. with c reative design technology and optim ization of component placement , these converters possess outstanding electrical and thermal performance, as well as extremely high reliability under highly stressful operating conditions.
ds_d c t 12s0a0s0 3 n fa _ 11142013 2 technical specificat ions ( t a = 25c, airflow rate = 300 lfm, v in = 4.5 vdc and 14 vdc, nominal vout unless otherwise noted.) parameter notes and conditions dc t 12s0a0s0 3 n fa min. typ. max. units absolute maximum ratings input voltage ( continuous ) - 0.3 15 v sequencing voltage - 0.3 vin max v ope rating ambient tem perature - 40 85 storage temperature - 55 125 input characteristics operating input voltage vo Q vin C 0. 6 4.5 14.0 v input under - voltage lockout turn - on voltage threshold 4.4 v turn - off voltage threshold 3. 2 v lockout hysteresis voltage 0.4 v maximum input current vin= 4.5 v to 14 v, io=io,max 3 .0 a no - load input current (vin = 12.0vdc, i o = 0, module enabled) v o ,set = 0.6 vdc 10 ma v o ,set = 3.3 vdc 25 ma off converter input current (vin = 12.0 vdc, module disabled) 0.8 ma inrush transient 1 a2s input reflected ripple current, peak - to - peak (5hz to 20mhz, 1h source impedance; v in =0 to 14 v, io= iomax ; 86 map - p output characteristics output voltage set point with 0.5% tolerance for external resistor used to set output voltage) - 1.5 vo,set +1.5 %vo,set output voltage adjustable range (sele cted by an external resistor) 0. 59 5.0 v output voltage regulation line(vin=vin, min to vin, max) for vo>=2.5v 0.4 % vo,set vo,set for vo<2.5v 10 mv load(i o =i o , min to i o , max) for vo>=2.5v 10 mv for vo<2.5v 5 mv temperature(tref=ta, m in to ta, max) for vo>=2.5v 0.4 %vo,set for vo<2.5v 5 mv total output voltage range over sample load, line and temperature - 2.5 + 2.5 %vo,set output voltage ripple and noise 5hz to 20mhz bandwidth peak - to - peak full load, 1f+10uf ceramic + 47uf ceramic 30 60 mv rms full load, 1f+10uf ceramic + 47uf ceramic 10 20 mv output current range 0 3 a output voltage over - shoot at start - up vout= 5.0 v 3 % vo,set output dc current - limit inception vin =12v 400 % io output short - circuit current (hicc up mode) io,s/c 0.5 adc dynamic characteristics dynamic load response 1 0f tan & 1f ceramic load cap, 2.5 a/s positive step change in output current 50% io , max to 100% io , max 150 mv negative step change in output current 100% io , max to 50% io , max 150 mv settling time to 1 0 % of peak deviation 20 s turn - on transient io=io.max start - up delay time, from on/off control time for von/off to vo=10% of vo,set 2 ms start - up delay time, from input time for vin=vin,min to vo=10% of vo,set 2 ms output voltage rise time time for vo to rise from 10% to 90% of vo,set 4 ms output capacitive load full load; esr R 0.15 m 47 800 f full load; esr R 10m 47 1800 f efficiency vo=5.0v vin=12v, 100% load 9 4. 9 % vo=2.5v vin=12v, 100% load 9 2.1 % vo=1.2v vin=12v, 100% load 8 6.5 % vo=0. 59 v vin=12v, 100% load 7 7.4 % feature characteristics swit ching frequency 600 khz on/off control, (negative logic) logic low voltage module on, von/off - 0.2 0.6 v logic high voltage module off, von/off 3.5 vin,max v logic low current module on, ion/off 10 a logic high current module off, ion/o ff 1 m a on/off control, (positive logic) logic high voltage module on, von/off 3.0 vin,max v logic low voltage module off, von/off - 0.3 0.6 v logic low current module on, ion/off 1 ma logic high current module off, ion/off 10 a tracki ng slew rate capability 0.1 2 v/msec tracking delay time delay from vin.min to application of tracking voltage 10 ms tracking accuracy power - up 2v/ms 100 mv power - down 1v/ms 100 mv general specifications mtbf io= 8 0% of io, max; ta=2 5c 17 m hours weight 1.6 grams
ds_d c t 12s0a0s0 3 n fa _ 11142013 3 characteristics curv es t he following figures provide converter efficiency versus output current figure 1 : converter efficiency vs. output current ( 5.0 vout) figure 2: converter efficiency vs. output current ( 3.3 vout) figure 3 : conv erter efficiency vs. output current ( 2.5vout) figure 4: converter efficiency vs. output current ( 1.8vout)
ds_d c t 12s0a0s0 3 n fa _ 11142013 4 figure 5: converter efficiency vs. output current ( 1.2vout) figure 6 : converter efficiency vs. output current ( 0.59vout ) t he following figu res provide t ypical output ripple and noise at 25 o c figure 7 : output ripple & noise at 12 vin, 5.0 v/ 3 a out ch1:vout, 20 mv/div , 1us/div figure 8 : output ripple & noise at 12 vin, 3.3 v/ 3 a out ch1:vout, 20 mv/div , 1us/div
ds_d c t 12s0a0s0 3 n fa _ 11142013 5 figure 9 : output ripple & noise at 12 vin, 2.5 v/ 3 a out ch1:vout, 20 mv/div , 1us/div figure 10 : output ripple & noise at 12 vin, 1.8 v/ 3 a out ch1:vout, 20 mv/div , 1us/div figure 11 : output ripple & noise at 12 vin, 1.2 v/ 3 a out ch1:vout, 20 mv/div , 1us/div figure 12 : output ripple & noise at 12 vin, 0.59 v/ 3 a out ch1:vout, 20 mv/div , 1us/div
ds_d c t 12s0a0s0 3 n fa _ 11142013 6 t he following figures provide t ypical start - up using input voltage at 25 o c figure 13 : turn on delay time at 12 vin, 5.0 v/ 3 a out ( top trace : vout, 2 v/div ; bottom trace : vin, 5 v /div ; 2ms/div ) figure 1 4 : turn on delay time at 12 vin, 3.3 v/ 3 a out ( top trace : vout, 1 v/div ; bottom trace : vin, 5 v/div ; 2ms/div ) figure 1 5 : turn on delay time at 12 vin, 2.5 v/ 3 a out top trace : vout, 1 v/div ; bottom trace : vin , 5 v/div ; 2 ms/div ) figure 1 6 : turn on delay time at 12 vin, 1.8 v/ 3 a out ( top trace : vout, 0.5 v/div, bottom trace : vin , 5 v/div ; 2ms/div )
ds_d c t 12s0a0s0 3 n fa _ 11142013 7 figure 1 7 : turn on delay time at 12 vin, 1.2 v/ 3 a out ( top trace : vout, 0.5 v/div ; bottom trace : vin , 5 v/div ; 2ms/d iv ) figure 1 8 : turn on delay time at 12 vin, 0.59 v/ 3 a out ( top trace : vout, 0. 2 v/div ; bottom trace : vin , 5 v/div ; 2ms/div ) t he following figures provide transient response to dynamic load change at 25 o c figure 1 9 : typical transient response to ste p load change at 1 a/s from 100% ~ 50% ~100% of io, max at 12 vin, 5.0 vout (cout = 1uf ceramic, 47uf+ 10f ceramic ) ch1 : vout, 50m v/div , 200us/div figure 20 : typical transient response to step load change at 1 a/s from 100% ~ 50% ~100% of io, max at 12 vin, 3. 3 vout (cout = 1uf ceramic, 47uf+ 10f ceramic ) ch1 : vout, 50m v/div , 200us/div
ds_d c t 12s0a0s0 3 n fa _ 11142013 8 figure 21 : typical transient response to step load change at 1 a/s from 100% ~ 50% ~100% of io, max at 12 vin, 2.5 vout (cout = 1uf + 47uf+ 10f ceramic ) ch1 : vout, 50m v/div , 200us/div figure 2 2 : typical transient response to step load change at 1 a/s from 100% ~ 50% ~100% of io, max at 12 vin, 1.8 vout (cout = 1uf + 47uf+ 10f ceramic ) ch1 : vout, 50m v/div ,200us/div figure 23 : typical transient response to step load chan ge at 1 a/s from 100% ~ 50% ~100% of io, max at 12 vin, 1.2 vout (cout = 1uf + 47uf+ 10f ceramic ) ch1 : vout, 50m v/div , 200us/div figure 24 : typical transient response to step load change at 1 a/s from 100% ~ 50% ~100% of io, max at 12 vin, 0.59 vout (cout = 1 uf + 47uf+ 10f ceramic ) ch1 : vout, 50m v/div , 200us/div
ds_d c t 12s0a0s0 3 n fa _ 11142013 9 t he following figures provide output short circuit current at 25 o c figure 2 5 : output short circuit current 12vin, 5.0vout top trace : vo, 1 v/div ; bottom trace : io , 5a/div; 20ms/div fig ure 2 6 : output short circuit current 12vin, 0.59 vout top trace : vo, 1 v/div ;bottom trace : io , 5a/div; 20ms/div t he following figures provide output short circuit current at 25 o c figure 2 7 : tracking func tion , vtracking= 5.5 v, vout= 5.0v, full load top trace :vtracking, 1 v/div ; bottom trace : vout, 1 v/div ;1ms/div figure 2 8 : tracking func tion , vtracking= 0.8 v,vout= 0.59 v, full load top trace : vtracking, 0.2 v/div ; bottom trace : vout, 0.2 v/div ; 1ms/div
ds_d c t 12s0a0s0 3 n fa _ 11142013 10 test configurations figure 2 9 : input reflected - ripple test setup note: use a 10f tantalum and 1f capacitor. scope measurement should be made using a bnc connector. figure 30 : peak - peak output noise and startup transient measurement test setup. figure 31 : output voltage and efficiency m easurement test setup note: all measurements are taken at the module terminals. when the module is not soldered (via socket), place kelvin connections at module terminals to avoid measurement errors due to contact resistance. design considerations input source impedance to maintain low noise and ripple at the input voltage, it is critical to use low esr capacitors at the input to the module. a highly inductive source can affect the stability of the module. an in put capacitance must be placed close to the modules input pins to filter ripple current and ensure module stability in the presence of inductive traces that supply the input voltage to the module. vo gnd 10uf tantalum 1uf ceramic scope resistive load v i vo gnd % 100 ) ( ? ? ? ? ii vi io vo ?
ds_d c t 12s0a0s0 3 n fa _ 11142013 11 design consideration s (con.) safety considerations for safet y - agency approval the power module must be installed in compliance with the spacing and separation requirements of the end - use safety agency standards. for the converter output to be considered meeting the requirements of safety extra - low voltage (selv), the input must meet selv requirements. the power module has extra - low voltage (elv) outputs when all inputs are elv. the input to these units is to be provided with a maximum 10 a fuse in the ungrounded lead. input under voltage lockout at input voltages below the input under voltage lockout limit, the module operation is disabled. the module will begin to operate at an input voltage above the under voltage lockout turn - on threshold. over - current protection to provide protection in an output over load f ault condition, the unit is equipped with internal over - current protection. when the over - current protection is triggered, the unit enters hiccup mode. the units operate normally once the fault condition is removed. features description s remote on/off the dc t series power module s have an on/off pin for remote on/off operation. both positive and negative on/off logic options are available in the dc t series power modules . for positive logic module, connect an open collector (npn) transistor or open drain (n channel) mosfet between the on/off pin and the gnd pin (see figure 32 ). positive logic on/off signal turns the module on during the logic high and turns the module off during th e logic low. when the positive on/off function is not used, leave the pin floating or tie to vin (modul e will be on) . for negative logic module, the on/off pin is pulled high with an external pull - up 5k figure 32 : positive remote on/off implementation figure 33 : negative remote on/off implementation vo o n/o ff v in gnd q1 rl i o n /o f f vo on/off vin gnd q1 rl rpull- up i o n /o ff
ds_d c t 12s0a0s0 3 n fa _ 11142013 12 features description s (con.) remote s ense th e dc t provide vo remote sensing to achieve proper regulation at the load points and reduce effects of distribution losses on output line. in the event of an open remote sense line, the module shall maintain local sense regulation through an interna l resistor. the module shall correct for a total of 0.5v of loss. the remote sense line impedance shall be < 10 ? figure 34 : effective circuit configuration for remote sense operation output voltage programming the output voltage of th e dc t can be p rogrammed to any voltage between 0. 59 vdc and 5.0 vdc by connecting one resistor (shown as rtrim in figure 35 ) between the trim and gnd pins of the module. without this external resistor, the output voltage of the module is 0. 59 vdc. to ca lculate the value of the resistor rtrim for a particular output voltage vo, please use the following equation: rtrim is the external resistor in k vo is the desired output voltage. for example, to program the output voltag e of th e d ct module to 5.0 vdc, rtrim is calculated as follows: figure 35 : circuit configuration for programming output voltage using an external resistor t able 1 provides rtrim values required for some common output voltages, by using a 0.5% tolerance trim resistor, set point tolerance of 1.5% can be achieved as specified in the electrical specification. table 1 certain restrictions apply on the output voltage set point depending on the input voltage. thes e are shown in the output voltage vs. input voltage set point area plot in fig ure 3 6 . the upper limit curve shows that for output voltages of 0.9v and lower, the input voltage must be lower than the maximum of 14v. the lower limit curve shows that for outp ut voltages of 3.8v and higher, the input voltage needs to be larger than the minimum of 4.5v. figure 36 : output voltage vs. input voltage set point area plot showing limits where the output voltage can be set for different input voltages. vo sense vin gnd rl distribution losses distribution losses distribution losses distribution losses ? ? ? ? ? ? ? ? ? k vo rtrim 591 . 0 91 . 5 ? ? ? ? ? ? ? ? ? ? ? k k rtrim 34 . 1 591 . 0 0 . 5 91 . 5 vo trim gnd rload rtrim vo(v) rtrim(k) 0.590 open 0.600 656.700 1.000 14.450 1.200 9.704 1.500 6.502 1.800 4.888 2.500 3.096 3.300 2.182 5.000 1.340
ds_d c t 12s0a0s0 3 n fa _ 11142013 13 when an analog volta ge is applied to the seq pin, the output voltage tracks this voltage until the output reaches the set - point voltage. the final value of the seq voltage must be set higher than the set - point voltage of the module. the output voltage follows the voltage on t he seq pin on a one - to - one basis. by connecting multiple modules together, multiple modules can track their output voltages to the voltage applied on the seq pin. for proper voltage sequencing, first, input voltage is applied to the module. the on/off pin of the module is left unconnected (or tied to gnd for negative logic modules or tied to vin for positive logic modules) so that the module is on by default. after applying input voltage to the module, a minimum 10msec delay is required before applying volt age on the seq pin. this delay gives the module enough time to complete its internal power - up soft - start cycle. during the delay time, the seq pin should be held close to ground (nominally 50mv 20 mv). this is required to keep the internal op - amp out of saturation thus preventing output overshoot during the start of the sequencing ramp. by selecting resistor r1 (see figure. 3 9 ) acc ording to the following equation figure 3 8 : sequential start - up t he voltage at the sequencing pin will be 50mv when the sequencing signal is at zero. feature des criptions (con.) voltage margining output voltage margining can be implemen ted in the dc t modules by connecting a resistor, r margin - up , from the trim pin to the ground pin for margining - up the output voltage and by connecting a resistor, r margin - down , f rom the trim pin to the output pin for margining - down. figure 3 7 shows the circuit configuration for output v olta ge margining. if unused, leave the trim pin unconnected. a calculation tool is available from the evaluation procedure which computes the value s of r margin - up and r margin - down for a specific output voltage and margin percentage . figure 3 7 : circuit configuration for output voltage margining output voltage sequencing th e dc t 12v 3 a modules include a sequencing feature, ez - sequence that enables users to implement various types of output voltage sequencing in their applications. this is accomplished via an additional sequencing pin. when not using the sequencing feature, either tie the seq pin to vin or leave it unconnecte d. ? ? ? ? ? ? ? ? ? 05 . 0 24950 1 vin r vo on/off vin gnd trim q2 q1 rmargin-up rmargin-down rtrim
ds_d c t 12s0a0s0 3 n fa _ 11142013 14 power good the dc t m odules provide a power good (pgood) signal that is implemented with an open - drain output to indicate that the output voltage is within the regulation limits of the power module. the pgood sig nal will be de - asserted to a low state if any condition such as over temperature, over current or loss of regulation occurs that would result in the output voltage going 10% outside the set point value. the pgood terminal should be connected through a pul l up resistor (suggested value 100k ) to a source of 5vdc or lower. monotonic start - up and shutdown th e dc t 3 a mo dules have monotonic start - up and shutdown behavior for any combination of rated input voltage, output current and operating temperature range. feature descriptions (con.) a fter the 10msec delay, an analog voltage is applied to the seq pin and the output voltage of the module will track this voltage on a one - to - one volt bases until the output reaches the set - point voltage. to initiate simultaneous shutdown of the modules, the seq pin voltage is lowered in a controlled manner. the output voltage of the modules tracks the voltages below their set - point voltages on a one - to - one basis. a valid input voltage must be maintained until the tracking and output voltages reach ground pot ential. when using the ez - sequencetm feature to control start - up of the module, pre - bias immunity during startup is disabled. the pre - bias immunity feature of the module relies on the module being in the diode - mode during start - up. when using the ez - seque ncetm feature, modules goes through an internal set - up time of 10msec, and will be in synchronous rectification mode when the voltage at the seq pin is applied. this will result in the module sinking current if a pre - bias voltage is present at the output o f the module. figure 3 9 : circuit showing connection of the sequencing signal to the seq pin. simultaneous
ds_d c t 12s0a0s0 3 n fa _ 11142013 15 thermal consideratio ns thermal management is an important part of the system design. to ensure proper, reliable operation, sufficient cooling of the power module is needed over the entire temperature range of the module. convection cooling is usuall y the dominant mode of heat transfer. hence, the choice of equipment to characterize the thermal performance of the power module is a wind tunnel. thermal testing setup deltas dc/dc power modules are characterized in figure 40 : wind tunnel test setup thermal derating heat can be removed by increasing airflow over the module. to enhance system reliability, the power module should always be operated below the maximum operating temperature. if the temperature exceeds the maximum module temperature, reliability of the unit may be affected. thermal curves figure 41 : temperature measurement location the all owed maximum hot spot tempera ture is defined at 1 20 figure 42 : output current vs. ambient tempera t ure and air velocity@vin= 12 v, vout= 5.0 v(either orientation) figure 43 : output current vs. ambient tempera t ure and air velocity@vin= 12 v, vout= 3.3 v(either orientation) air flow module pwb 50.8(2.00") air velocity and ambient temperature sured below the module fancing pwb note: wind tunnel test setup figure dimensions are in millimeters and (inches) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 55 60 65 70 75 80 85 90 95 100 105 output current(a) ambient temperature ( ) DCT12s0a0s03 output current vs. ambient temperature and air velocity @vin=12v vout=5.0v (either orientation) natural convection 100lfm 200lfm 0.0 0.5 1.0 1.5 2.0 2.5 3.0 55 60 65 70 75 80 85 90 95 100 105 output current(a) ambient temperature ( ) DCT12s0a0s03 output current vs. ambient temperature and air velocity @vin = 12v vout=3.3v ( either orientation ) 100lfm natural convection
ds_d c t 12s0a0s0 3 n fa _ 11142013 16 figure 4 4 : output current vs. ambient tempera t ure and air velocity@vin= 12 v, vout= 2.5 v(either orientation) figure 4 5 : output current vs. ambient tempera t ure and air velocity@vin= 12 v, vout= 1.8 v(either orientation) figure 4 6 : output current vs. ambient tempera t ure and air velocity@vin= 12 v, vout= 1.2 v(either orientation) figure 4 7 : output current vs. ambient tempera t ure and air velocity@vin= 12 v, vout= 0. 59 v(either orientation) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 55 60 65 70 75 80 85 90 95 100 105 output current(a) ambient temperature ( ) DCT12s0a0s03 output current vs. ambient temperature and air velocity @vin = 12v vout=2.5v(either orientation) natural convection 100lfm 0.0 0.5 1.0 1.5 2.0 2.5 3.0 55 60 65 70 75 80 85 90 95 100 105 output current(a) ambient temperature ( ) DCT12s0a0s03 output current vs. ambient temperature and air velocity @vin = 12v vout=1.8v(either orientation) natural convection 100lfm 0.0 0.5 1.0 1.5 2.0 2.5 3.0 55 60 65 70 75 80 85 90 95 100 105 output current(a) ambient temperature ( ) DCT12s0a0s03 output current vs. ambient temperature and air velocity @vin = 12v vout=1.2v(either orientation) natural convection 100lfm 0.0 0.5 1.0 1.5 2.0 2.5 3.0 55 60 65 70 75 80 85 90 95 100 105 output current(a) ambient temperature ( ) DCT12s0a0s03 output current vs. ambient temperature and air velocity @vin = 12v vout=0.59v(either orientation) natural convection
ds_d c t 12s0a0s0 3 n fa _ 11142013 17 pick and place locat ion recommended pad layo ut surface - mount tape & reel
ds_d c t 12s0a0s0 3 n fa _ 11142013 18 lead (sn/pb) process recommend te mp. profile note: the temperature refers to the pin o f dc t , m easured on the pin vout joint. lead free (sac) proc ess recommend temp. profile note: the temperature refers to the pin of dc t , me asured on the pin vout joint. temp . time 150 200 90~120 sec. time limited 75 sec. above 220 220 preheat time ramp up max. 3 ramp down max. 4 peak temp. 240 ~ 245 25
ds_d c t 12s0a0s0 3 n fa _ 11142013 19 mec hanical drawin g
ds_d c t 12s0a0s0 3 n fa _ 11142013 20 part numbering syste m d c t 12 s 0a0 s 0 3 n f a produ ct series input voltage numbers of outputs output voltage package type output current on/off logic option code DCT - 3a d c s - 6a d c m - 1 2 a d c l - 20 a 04 - 2. 4 ~5.5v 1 2 C 4.5 ~14v s - single 0a0 - programmable s - smd 03 - 3a 06 - 6 a 1 2 - 1 2 a 20 - 20 a n - n egative p - positive f - rohs 6/6 (lead free) a - s tandard fun c tion model list model name packaging input voltage output voltage o utput current efficiency 12 vin, 5 v dc @ 3 a d c t 12 s0a0s0 3 nfa smd 4.5 ~ 14 vdc 0 . 59 v ~ 5. 0 vdc 3 a 9 4. 9 % c ontact: www.deltaww.com/dcdc usa: telephone: east coast: 978 - 656 - 3993 west coast: 510 - 668 - 5100 fax: (978) 656 3964 email: dcdc@delta - corp.com europe: telephone: +31 - 20 - 655 - 0967 fax: +31 - 20 - 655 - 0999 email: dcdc@delta - es. com asia & the rest of world : telephone: +886 3 4526107 ext. 6220~6224 fax: +886 3 4513485 email: dcdc@delta.com.tw warranty delta offers a two ( 2) year limited warranty. complete warranty information is listed on our web site or is available upon request from delta. information furnished by delta is believed to be accurate and reliable. however, no responsibility is assumed by delta for its use, nor for any infringements of patents or other rights of third parties, which may result from its use. no licens e is granted by implication or otherwise under any patent or patent rights of delta. delta reserves the right to revise these specifications at any time, without notice .

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